Name     2registers ; 
PartNo   any ; 
Date     05/06/2024 ;
Revision 02 ;
Designer Engineer ;
Company  None ;
Assembly None ; 
Location  ;
Device  f1504isptqfp100;


/* 

***** PWR, NC, JTAG *****

Pin 1  = NC;
Pin 2  = NC;
Pin 3  = VCC;
Pin 4  = TDI; 
Pin 5  = NC;
Pin 7  = NC;
Pin 11 = GND;
Pin 15 = TMS;  
Pin 18 = VCC;
Pin 22 = NC;
Pin 24 = NC;
Pin 26 = GND;
Pin 27 = NC;
Pin 28 = NC;
Pin 34 = VCC;
Pin 38 = GND;
Pin 39 = VCC;
Pin 43 = GND;
Pin 49 = NC;
Pin 50 = NC;
Pin 51 = VCC;
Pin 53 = NC;
Pin 55 = NC;
Pin 59 = GND;
Pin 62 = TCK;  
Pin 66 = VCC;
Pin 70 = NC;
Pin 72 = NC;
Pin 73 = TDO;  
Pin 74 = GND;
Pin 77 = NC;
Pin 78 = NC;
Pin 82 = VCC;
Pin 86 = GND;
Pin 91 = VCC;
Pin 95 = GND;

***** I/O pins *****

Pin 6  = IO_1; 
Pin 8  = IO_2; 
Pin 9  = IO_3; 
Pin 10 = IO_4; 
Pin 12 = IO_5; 
Pin 13 = IO_6; 
Pin 14 = IO_7; 
Pin 16 = IO_8;  
Pin 17 = IO_9;  
Pin 19 = IO_10;  
Pin 20 = IO_11;  
Pin 21 = IO_12;  
Pin 23 = IO_13;  
Pin 25 = IO_14;  
Pin 29 = IO_15;  
Pin 30 = IO_16;  
Pin 31 = IO_17;  
Pin 32 = IO_18;  
Pin 33 = IO_19;  
Pin 35 = IO_20;  
Pin 36 = IO_21;  
Pin 37 = IO_22;  
Pin 40 = IO_23;  
Pin 41 = IO_24;  
Pin 42 = IO_25;  
Pin 44 = IO_26;  
Pin 45 = IO_27;  
Pin 46 = IO_28;  
Pin 47 = IO_29;  
Pin 48 = IO_30;  
Pin 52 = IO_31;  
Pin 54 = IO_32;  
Pin 56 = IO_33;  
Pin 57 = IO_34;  
Pin 58 = IO_35;  
Pin 60 = IO_36;  
Pin 61 = IO_37;  
Pin 63 = IO_38;  
Pin 64 = IO_39;  
Pin 65 = IO_40;  
Pin 67 = IO_41;  
Pin 68 = IO_42;  
Pin 69 = IO_43;  
Pin 71 = IO_44;  
Pin 75 = IO_45;  
Pin 76 = IO_46;  
Pin 79 = IO_47;  
Pin 80 = IO_48;  
Pin 81 = IO_49;  
Pin 83 = IO_50;  
Pin 84 = IO_51;  
Pin 85 = IO_52;  
Pin 92 = IO_53;  
Pin 93 = IO_54;  
Pin 94 = IO_55;  
Pin 96 = IO_56;  
Pin 97 = IO_57;  
Pin 98 = IO_58;  
Pin 99 = IO_59;  
Pin 100 = IO_60; 

***** Input Only ****

Pin 87 = xIO_61; /* INPUT/GCLK1 /
Pin 88 = xIO_62; /* INPUT/OE1 - 12V Vpp/
Pin 89 = xIO_63; /* INPUT/GCLR /
Pin 90 = xIO_64; /* INPUT/OE2/GCLK2 /

*/

/* Start Here */
 
PIN     
[ 6 , 8 , 9 , 10 , 12 , 13 , 14 , 16 , 17 , 19 , 20 , 21 , 23 , 25 , 29 , 30]
	= [A15..A0];     /*  I; active high      CPU address bus */
PIN     
[ 31 , 32 , 33 , 35 , 36 , 37 , 40 , 41]
	= [D0..D7];      /*  I; active high      CPU data bus */
PIN     
87 /* INPUT/GCLK1 */
	= E       ;      /*  I; active high      E CPU.34                System clock */
PIN 
89	/* INPUT/GCLR */
	= !Reset; 

PIN     
81
	= Rw      ;      /*  I; active high      R/~{W} CPU.32   1=Read; 0=Write */

PIN     
99
	= !RAM0_CS;      /*  O; active low       Chip select for RAM0 */
PIN     
98
	= !RAM1_CS;      /*  O; active low       Chip select for RAM1 */
PIN     
97
	= !RAM2_CS    ;  /*  O3; active low      Chip select for RAM2 */
PIN     
96
	= !RAM3_CS    ;  /*  O3; active low      Chip select for RAM3 */


PIN     
83
	= !RAM01_OE;     /*  O; active low       Read qualified by E     For RAM0, RAM1 */
PIN     
84
	= !RAM01_WE;     /*  O; active low       Write qualified by E    For RAM0, RAM1 */

RAM01_OE        = E & Rw;
RAM01_WE        = E & !Rw;

/* LED Output */
PIN   
100
	= LED;          /* LED output */



/* Internal Registers */
FIELD ADDRESS = [A15..A0];
/* FIELD DATA = [D7..D0]; */
PINnode = [REGA7..0];
PINnode = [REGB7..0];
/*
FIELD RA = [REGA7..0];
FIELD RB = [REGB7..0];
*/

/* Equations */
[D0..7] = 		(ADDRESS:C080) & [REGA0..7] #
		  		(ADDRESS:C081) & [REGB0..7];
[D0..7].oe = 	E & Rw & (ADDRESS:C080) #
           		E & Rw & (ADDRESS:C081);
           		
[REGA0..7].D = 	[D0..7];
[REGA0..7].CK = E;
[REGA0..7].CE = !Rw & (ADDRESS:C080);
[REGA0..7].AR = Reset;

[REGB0..7].D = 	[D0..7];
[REGB0..7].CK = E;
[REGB0..7].CE = !Rw & (ADDRESS:C081);
[REGB0..7].AR = Reset;


/* LED Equation */
LED = (ADDRESS: C080)#(ADDRESS: C081);

/* Global Clear */

/*[REGA0..7],REGB = !RESET;*/
RAM0_CS		=  !A15;
RAM1_CS		=   A15 & !( (ADDRESS:C0XX) & ( A7:00 # [A7..1]:81 ) );  /* and not any device nor register*/
RAM2_CS		=  'b'0;	/* not now */
RAM3_CS		=  'b'0;	/* not now */

pin 67 = test_read;
test_read =   E & Rw;
pin 80 = test_write;
test_write =   E & !Rw;